In one aspect of the related art, a process for converting an analog signal into a digital signal comprises measuring the amplitude of the analog signal at consistent time intervals and producing a set of signals representing the measured digital value. ADCs are well known in the art. One type of analog-to-digital converter uses a single comparator to successively compare an input signal to multiple reference signals. This type of ADC, while inexpensive, is inherently slow since the single comparator must make a number of successive comparisons in order to convert each analog sample into a digital output
A Flash ADC (also known as parallel ADCs, or a direct-conversion ADC) provides a faster way to convert an analog signal to a digital signal. A Flash ADC uses a linear voltage ladder with a comparator at each “rung” of the ladder to compare the input voltage to successive reference voltages. Often these reference ladders are constructed from resistors. However alternative implementations may employ capacitive voltage division. The output of these comparators is typically coupled into a digital encoder which converts the inputs into a binary value.
The Flash ADC architecture is relatively simple. Aside from the comparators, it only requires logic for the final conversion to binary. However, a Flash ADC requires a large number of comparators compared to other ADCs, especially as the precision increases. A Flash ADC requires 2n−1 comparators for an n-bit conversion. While Flash ADCs are ideal for applications requiring very large bandwidth, due to their large number of comparators, they consume more power than other ADC architectures.
Therefore, there is a need in the art for an ADC architecture that provides the performance advantages of a Flash ADC while providing for lower power consumption.